How to Initialize BRAM with COE file for Xilinx FPGA

Many people have asked me this question recently so I figure it might be worth to write it down to benefit a larger audience.

Here are the steps you need to take.

Step 1: Create COE file for the data from Memory Editor.

In the recent ISE versions, the Memory Editor is removed from menu options and you need to run a script “mem_edit” from the command line window.

For Linux user:

First setup the system environment variables with script: [Installation dir]/ISE_DS/settings64.csh

Then run the mem_edit from [Installation dir]/ISE_DS/ISE/bin/lin64/mem_edit

The Memory Editor window looks like this. You can simply edit the values in the GUI.

For Windows Users:

You can run the mem_edit.bat from the “ISE command window”. Run from ISE command window instead of the regular system command window is important.

After you are done with the editing, goto “File->Generate” to generate the COE file. The COE file is used in CoreGen to create the MIF file. After that, it is not needed for synthesis and FPGA creation.

Step 2: Generate the BRAM with CoreGen

You can generate ROM or RAM with the BRAM and with initial values. Just specify the COE file as the initial file in Step 4 of Block Memory Generator.

After you click the “Generate”, the CoreGen will create the verilog model as well as MIF file.

The BRAM module with and without INIT_FILE are compared below.

The MIF file is actually a pure text file. So if you need to update ROM content, it is actually very efficient to use a script file to re-generate the MIF file only.

The files used in this article is attached here for your reference.

Step 3: Synthesis and Create Your FPGA build

Nothing special is required for this step.

Good luck and let us know how it works for you.