SWD (serial wire debug) is a debug interface ARM provided in replacement of the usual JTAG interface. The advantage is obvious: 2 wires needed vs. 4 wires. If you want to instantiate the ARM core in FPGA with SWD interface.
Many people have asked me this question recently so I figure it might be worth to write it down to benefit a larger audience. Here are the steps you need to take. Step 1: Create COE file for the data