SWD (serial wire debug) is a debug interface ARM provided in replacement of the usual JTAG interface. The advantage is obvious: 2 wires needed vs. 4 wires. If you want to instantiate the ARM core in FPGA with SWD interface. Here is how you do it.
1. Declare Pin signals
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inout SWDIO, input SWCLK, |
2. Config the ARM core to use SWD instead of JTAG.
It is usually through a compile time parameter setting.
3. Connect the signals
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wire TCK; // Optional BUFR for SWCLK, may help in timing BUFR TCLK_BUF( .CE(1'b1), .CLR(1'b0), .O (TCK), .I (SWCLK)); assign swclk = TCK ; assign swdi = SWDIO ; bufif1 (SWDIO, swdo, swden) ; PULLUP U_SWDIO (SWDIO); |
Pretty simple, right? Let us know how it works for you.
How to Instantiate ARM core with SWD in FPGA